1. The Field of the Invention
This invention relates to computer systems and, more particularly, to novel systems and methods for real-mode addressing of computer memory above the one megabyte limit currently imposed by real-mode operating systems, and without resorting to protected-mode operating systems with their inherent complexity and overhead.
2. The Background Art
Computers relying on processors (CPUs) such as the X86 family of Intel processors, may operate in real mode or protected mode. Real-mode operating systems rely on 16-bit addressing. Protected-mode operating systems operate with 32-bit addressing. Real-mode addressing schemes may not create and use addresses greater than 20 bits, corresponding to approximately one megabyte of address space. Address space is simply a number in a mathematical space, but limits the ability of a processor to access the random access memory (RAM) or other memory above one megabyte.
One may think of "real-mode" addressing as 20-bit addressing. Should 4 gigabytes (a 32-bit number) of memory become available, a 20-bit addressing scheme cannot address more than about 1 megabyte of the 32-bit address space. Thus, in real mode, only approximately one four-thousandth of the total available memory or address space could actually be accessed by the processor.
Protected-mode operating systems may use addresses up to 32 bits, corresponding to approximately four gigabytes of memory. Operation in protected mode may provide descriptor tables resident in memory. The descriptor tables may include a global descriptor table (GDT), a local descriptor table (LDT), and an interrupt descriptor table (IDT). Each descriptor table contains descriptors. A descriptor may be thought of as one row of a table, for example. Within each descriptor (row) may be an access rights field, a base physical address field, and a segment length field.
During operation of a processor, the contents of a particular descriptor in any particular descriptor table (e.g., GDT, LDT, or IDT) may be loaded into a hidden cache descriptor register associated with a particular segment register of the processor. The processor relies on the hidden cache descriptor registers to perform the processor's addressing function. Since protected mode permits 32-bit addressing, the hidden cache descriptor registers must also contain sufficient capability to support 32-bit addressing.
However, in real mode, the hidden cache descriptor registers are limited by the real-mode loading scheme. Any time a segment register is loaded in real mode, a corresponding hidden cache descriptor register is loaded with values that limit the addressing functionality thereof.
For example, the base address will never be greater than a 20-bit value. The segment length may never be larger than a 16-bit value. Likewise, the access rights are set in accordance with the limitations and operations of real mode. The D/B bit is set to 16-bit addressing. Also, the access rights for the code segment register, data segment register, and the other segment registers, may all have a common value allowing all segments to have read, write, and execute access for the processor with respect to all segments.
By contrast, in protected mode, code segments are typically limited to read access and execute access only. Data segments may typically be limited to read access and write access, with no execute access permitted. The extra segment register, stack segment register, FS register and GS registers are typically treated as data registers.
Thus, in protected mode, certain operations by the processor are protected. Instead, real-mode operation allows all operations for all segments. Real mode is sometimes seen as a free-for-all that may destroy code or data without security measures intervening.
The price for protected mode may be paid in several ways, or exacted in several ways. From a programming perspective, the addressing model is much more complex than that for real mode Accordingly, addressing schemes are more complex to program. Thus, operating systems become substantially more complex to accommodate the protection mechanism implemented by the various descriptor tables (GDT, LDT, IDT). From a processor's point-of-view, management of the descriptor tables becomes substantial. A 15% degradation in performance is typical to support the loading and unloading of the hidden cache descriptor registers from the descriptors contained in any appropriate descriptor table.
What is needed, is an apparatus and method for achieving the addressing capability of a protected-mode operating system, without the attendant overhead and commensurate degradation of performance. Certain protections provided by a protected-mode operating system are desirable, and should be maintained. Thus, a real-mode 32-bit, flat-model execution is needed.